The present invention relates to graphics processing, and more particularly, to vertex data compression method and apparatus for compressing vertex data through analyzing channel properties and related vertex data decompression method and apparatus.
As known in the art, graphics processing is typically carried out in a pipelined fashion, with multiple pipeline stages operating on the data to generate the final rendering output (e.g., a frame that is displayed). Many graphics processing pipelines now include one or more programmable processing stages, commonly referred to as “shaders”, which execute programs to perform graphics processing operations to generate the desired graphics data. For example, the graphics processing pipeline may include a vertex shader and a pixel (fragment) shader. These shaders are programmable processing stages that may execute shader programs on input data values to generate a desired set of output data values for being further processed by the rest of the graphics pipeline stages. The shaders of the graphics processing pipeline may share programmable processing circuitry, or may be distinct programmable processing units.
For example, the vertex shading operation may include a vertex position shading operation and a vertex attribute shading operation for vertices of primitives in each frame. With regard to a deferred rendering scheme (e.g., a bin-based rendering scheme), a conventional design is to perform the vertex position shading operation and the vertex attribute shading at the binning process (i.e., vertex phase (VP) pass) and store the vertex position shading results and the vertex attribute shading results of vertices of all primitives in the frame into a bin memory, and then performs the pixel/fragment shading operation at the rendering process (i.e., pixel phase (PP) pass) after the binning process is done. Since the bin memory is needed to store vertex position shading results and vertex attribute shading results of many vertices, the memory traffic and the memory space requirement is large. In addition, the data traffic written by VP and read by PP may cause the performance drop of the deferred rendering scheme.
Thus, there is a need for an innovative vertex data compression design which is capable of saving the memory traffic and the memory space requirement.